This invention relates to a sense amplifier for a semiconductor device, in particular, to a memory device for a multi-level memory in which each memory cell stores data represented by a plurality of binary bits.
A concept for multi-level memories has been proposed as a breakthrough in the capacity limitation problem of semiconductor memory devices. (Electronics, October, 1980, p. 39, ibid. June 30, 1982, p. 81, etc.). This technique increases the capacity of a memory device, having a constant chip size, without increasing integration density. Some four-level type memory devices have been put into practical application as ROMs (Read Only Memories). In the ROMs, the level of the read out signal from each memory cell is related to one of the four states (data) represented by two binary bits. This data is usually written as the difference in the conductivity of the MOS transistor forming a memory cell, during the manufacturing process of the memory device by altering the size of the gate area of each transistor. Therefore, the ROM is categorized as a mask ROM.
In the case of a four-level memory device, the level of each read-out signal is compared with three reference voltages, accordingly, it is necessary to have at least three sense amplifiers each of which receives one of the three different reference voltages. FIG. 1 is a partial circuit diagram of a four-level ROM device, showing a memory cell M.sub.C and a sensing circuit including a load circuit LOAD, a column select transistor Q.sub.C, and three sense amplifiers, SA.sub.1, SA.sub.2 and SA.sub.3, whose inputs are commonly connected to the data bus. In FIG. 1, Q.sub.D1 is a transistor for discharging the bit line prior to the selection of column and row. As seen in FIG. 1, when the gate of LOAD is opened and the column select signal COL and row select signal ROW are respectively applied to each gate of the transistor Q.sub.C and the memory cell M.sub.C, a readout signal of a specified level corresponding to the data stored in the memory cell M.sub.C is generated on the data bus and applied to the sense amplifiers SA.sub.1, SA.sub.2 and SA.sub.3, simultaneously.
Sense amplifiers typically employed for memory devices are classified into two kinds; one is a type of differential amplifier, and the other comprises a flip-flop circuit. A sense amplifier of the former type for sensing a multiple bit ROM is disclosed in U.S. Pat. No. 4,287,570 for instance. In view of sensitivity, a sense amplifier of the flip-flop type is more advantageous than a differential amplifier type, however, it seems that no flip-flop type sense amplifier which can be used for a multi-level memory device has been disclosed. Though there are many disclosures of flip-flop type sense amplifiers for the use in RAMs (Random Access Memories), they can not be employed in multi-level memory devices, because of the following problem.
In a RAM, each input signal is two levels, and the sense amplifier is only required to discriminate read-out signals whose levels change within a narrow range such as about 1 volt below the power source voltage. On the other hand, in the four-level memory device, for example, three sense amplifiers must respond to four-level input signals over a range of a few voltage, and it is necessary to provide means to isolate each flip-flop type sense amplifier to function independently from the others. Further, the solutions for these problems formerly resulted in an increase in operational delay in the flip-flop type sense amplifiers, particularly in those for ROMs.